1. Field of the Invention
The present invention relates to the protection of input/output terminals of an integrated circuit against electrostatic discharges (ESD). Such protections are generally provided on the pads of an integrated circuit and consist of connecting these pads to a reference voltage (generally, the ground) to carry off a possible electrostatic discharge. A point in an electronic circuit sensitive to electrostatic discharges can also be protected.
2. Discussion of the Related Art
FIG. 1 is a schematic and simplified block diagram of a circuit 1 for protecting an input/output stage 2 (I/O) of an integrated function 3 (FCT). In FIG. 1, the input/output stage is assumed to be connected on the one hand to a pad 4, the entire circuit (2+3) being further connected to a pad 5 representing a reference voltage (here, ground GND).
A protection device 1 is essentially formed of a switch, generally unidirectional, directly connecting pad 4 to ground 5. This switch is controlled upon occurrence of an electrostatic discharge on pad 4 of the integrated circuit. This control is illustrated in FIG. 1 by a dotted line ESD.
In MOS technology integrated circuits, the occurrence of an electrostatic discharge is often detected by an N-channel MOS transistor having its drain defining anode A of switch 1 connected to pad 4 and having its source connected to the gate and defining grounded cathode K
FIG. 2A shows a first known example of an ESD protection switch 1. The switch is an N-channel MOS transistor M1 having its gate G, source S, and bulk B interconnected and defining cathode K of the switch and having its drain D forming anode A. In fact, the presence of an electrostatic discharge starts an NPN bipolar transistor intrinsic to the MOS transistor. This transistor is shown in dotted lines in FIG. 2A by its equivalent electric diagram. It is an NPN transistor having its collector corresponding to drain D of transistor M1, having its emitter corresponding to source S of transistor M1, and having its base corresponding to bulk B of transistor M1.
The protection capacity of switch 1 depends on the size of transistor M1. In practice, this protection capacity generally is on the order of a few tens of volts per micrometer of gate width of transistor M1.
FIG. 2B shows a second known example of an ESD protection switch 1′. Here, a transistor M1′, connected like transistor M1 of FIG. 2A, is associated with a cathode-gate thyristor THK having its anode connected to the drain of transistor M1′ (anode A of switch 1′) and having its cathode connected to the source of transistor M1′ (cathode K of switch 1′). Gate G of thyristor THK is connected to the source (and thus to the gate) of transistor M1′. In FIG. 2B, thyristor THK has been symbolized in the form of a PNP transistor 11 and of an NPN transistor 12 in usual fashion. The emitter of the PNP transistor defines anode A of the thyristor and its collector is connected to the base of transistor 12 which defines gate G′ of the thyristor. The base of PNP transistor 11 is connected to the collector of NPN transistor 12 and the emitter of the latter defines cathode K of the thyristor, a resistor R connecting the gate to the cathode to enable starting of the thyristor.
The structure of FIG. 2B enables decreasing the size of MOS transistor M1′ for a same protection capacity, a thyristor being generally able to stand on the order of 100 volts per micrometer of width.
The function of transistors 11 and 12 forming the thyristor is the same as that of the parasitic bipolar transistor of the MOS transistor, that is, absorbing the current of the electrostatic discharge and thus avoiding damaging the gate of the MOS transistor.
A disadvantage of the conventional ESD protection switches of FIGS. 2A and 2B is linked to a manufacturing parameter of N-channel MOS transistor M1 or M1′ in so-called low-cost technologies. This parameter is the so-called GIDL parameter (Gate Induced Drain Leakage) which corresponds to a current leakage between the drain and the gate of the MOS transistor. This leakage appears as soon as a voltage is applied between the drain and the source of the MOS transistor (and thus between the gate and the drain, since the gates and sources are here interconnected). The occurrence of this leakage turns on the MOS transistor before it has been able to turn on its parasitic bipolar NPN transistor. Accordingly, this bipolar transistor remains off and the magnitude of the current (the electrostatic discharge) damages the actual MOS transistor.